Microchip 24LC128 128K I2C Serial EEPROM: Features and Application Design Guide
The Microchip 24LC128 is a 128-Kilobit (16-KByte) serial Electrically Erasable Programmable Read-Only Memory (EEPROM) that supports the I2C (Inter-Integrated Circuit) protocol. It serves as a fundamental component for non-volatile data storage in a vast array of microcontroller-based systems, from consumer electronics to industrial automation. Its combination of capacity, ease of use, and reliability makes it a perennial choice for designers.
Key Features of the 24LC128
The 24LC128 distinguishes itself through a set of robust features tailored for flexible integration and dependable performance.
I2C Serial Interface: The device communicates via a simple, two-wire I2C bus (Serial Clock - SCL and Serial Data - SDA), significantly reducing the number of I/O pins required from the host microcontroller compared to parallel alternatives.
High Capacity: Organized as 16,384 x 8 (16K x 8), it provides ample space for storing system parameters, calibration data, user settings, and transaction logs.
Wide Voltage Operation: It operates across a broad voltage range (1.7V to 5.5V), making it compatible with various logic levels and ideal for both 5V and modern low-power 3.3V systems, as well as battery-powered applications.
Page Write Capability: The memory is configured in 64-byte pages, allowing for faster write operations by writing a full page of data in a single write cycle, which is more efficient than writing individual bytes.
Software Write Protection: The entire memory array can be write-protected using the WC (Write Control) pin. When held low, writes are enabled; when driven high, the entire memory is protected from inadvertent write operations, enhancing data integrity.
High Reliability: The 24LC128 is specified for 1,000,000 erase/write cycles per byte and offers >200 years of data retention, ensuring long-term data integrity.
Application Design Guide
Successfully integrating the 24LC128 into a design requires attention to several key hardware and software considerations.
1. Hardware Interfacing:
The connection to a microcontroller is straightforward. The SCL and SDA lines must be connected to the corresponding pins on the MCU. These lines require pull-up resistors (typically 4.7kΩ for 400 kHz, though value depends on bus speed and capacitance) to keep them at a logic high when no device is pulling them low. The address pins (A0, A1, A2) are used to set the device's I2C address, allowing up to four 24LC128 devices to coexist on the same bus. The WC pin should be tied to VSS or controlled by a GPIO for protection.
2. Device Addressing:
After a START condition, the master transmits a control byte. The first four bits are fixed as 1010 for this device family. The next three bits (A2, A1, A0) are set by the hardware pin levels. The final bit is the Read/Write (R/W) select bit; '1' indicates a read operation, and '0' indicates a write operation.
3. Write Operations:
Byte Write: The master sends the control byte (R/W=0), followed by a 16-bit memory address (two bytes) and the single data byte to be written.
Page Write: The master sends the control byte (R/W=0), the 16-bit starting address, and then up to 64 bytes of data. The internal address pointer auto-increments after each data byte is received. If the end of the page is reached, the pointer wraps around to the start of the same page, potentially overwriting previous data.
4. Read Operations:
Current Address Read: The internal address pointer's last value is used. The master sends a control byte (R/W=1) and reads the next byte.
Random Read: The master first performs a dummy write operation to set the address pointer: it sends the control byte (R/W=0) followed by the desired 16-bit address. It then issues a START condition again and sends the control byte (R/W=1) to read the data.
Sequential Read: After any read operation, the master can continue to read bytes. The internal address pointer automatically increments after each byte is transmitted, allowing the entire memory to be read in one continuous operation.
5. Critical Timing Considerations:
Designers must account for the write cycle time (t_WC). After a write command is acknowledged, the device enters an internally timed write cycle (typically 5ms max) during which it will not respond to its address. The master must poll the device by sending a START and the control byte until the device acknowledges, indicating the write cycle is complete and the device is ready for a new command.
ICGOOODFIND
The Microchip 24LC128 remains an industry-standard I2C EEPROM due to its proven reliability, simple two-wire interface, and sufficient density for countless applications. Its built-in write protection and wide voltage range make it an exceptionally versatile and robust solution for non-volatile data storage needs. Careful design, particularly regarding pull-up resistors, addressing, and write cycle timing, ensures optimal performance and data integrity in the final product.
Keywords: I2C Interface, Non-Volatile Memory, Page Write, Write Protection, EEPROM.
